1. Field of the Invention
The present invention relates to a method of effectively compressing a test vector required for testing a system-on-chip (SOC) semiconductor device. The present invention is the result of efforts to foster and support university IT research centers, carried out by the Ministry of Information and Communication in Republic of Korea.
2. Related Prior Art
With the development of semiconductor design techniques, a system-on-chip (SOC) configuration, in which functional blocks are integrated into a single chip, can be manufactured. In order to test semiconductor devices in such a high-performance SOC, the number and complexity of test vectors to be input are increased and automatic test equipment (ATE) requires a high operating frequency and a large memory capacity. This increases time and cost required for testing the semiconductor devices. Accordingly, people have a growing interest in the compression of test vectors. The compression of the test vector enables effective utilization of a restricted channel of the ATE.
The test vector used when a semiconductor device is tested has a large number of similar bits. Thus, the test vector can represent only values that are different from each other when the exclusive-OR operation (XOR) is carried out on the bits of the test vector. This is because the elusive-OR operation outputs ‘0’ when the input bits are identical to each other but outputs ‘1’ when the input bits are different from each other. The original test vector Td and a test set Tdiff are defined as follows:Td={t1, t2, t3, t4, t5, . . . , tn}Tdiff={d1, d2, d3, . . . , dn}={t1, t1⊕t2, t2⊕t3, . . . ,tn−1⊕tn}
According to this method, only the bits of the test vector that have different values from the corresponding bits of the previous element are represented by ‘1’. Thus, most of values of Tdiff are continuous ‘0’s considering that the test vector is characterized by having a large number of identical bits.
The vector Tdiff generated as above is connected in a single chain as follows:Tdiff: d1=00000100d2=00110000d3=00010001=>000001000011000000010001
The point where the bit ‘1’ first appears in the chain is checked and the number of digits of ‘0’ appearing before the bit ‘1’ is counted to generate a codeword through a method represented by Table 1.
TABLE 1CodewordTdiff000100101010001011000110000001101000001110000000111100000001
The generated data is stored in the ATE for use. A corresponding circuit receives the compressed codeword and decompresses the compressed codeword to use it. A decompression device used for decompressing the codeword is illustrated in FIG. 1. A cyclical scan register (CSR) can obtain the current test vector from Tdiff by applying XOR to Tdiff again. Using this process, the original test vector can be completely restored using only a single decoder.
However, as semiconductor device chips are configured as system-on-chips, the number of test vectors increases and the number of vectors having identical bits also increases. Accordingly, the conventional algorithm cannot effectively compress an increasing number of test sets for a circuit. Furthermore, a conventional statistical code compression technique increases hardware overhead and cannot make functional blocks for tests in a circuit large. There is therefore a need for a new compression technique capable of obtaining a high compression ratio using simple hardware.